1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a switching element having a sunken gate electrode of an array substrate for a liquid crystal device and a fabricating method thereof.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal molecules. The liquid crystal molecules have a definite orientational order in alignment resulting from their thin and long shapes. The alignment direction of the liquid crystal molecules can be controlled by applying an electric field to the liquid crystal molecules. In other words, as the intensity of the electric field is changed, the alignment of the liquid crystal molecules also changes. Since incident light through liquid crystal is refracted based on an orientation of the liquid crystal molecules, due to the optical anisotropy of the aligned liquid crystal molecules, intensity of the incident light can be controlled and images can be displayed.
Among the various types of LCD devices commonly used, active matrix LCD (AM-LCD) devices having thin film transistors (TFTs) and pixel electrodes connected to the TFTs disposed in matrix form, have been developed because of their high resolution and superiority in displaying moving images.
FIG. 1 is a schematic perspective view of a liquid crystal display device according to the related art. In FIG. 1, a liquid crystal display (LCD) device 11 includes a first substrate 5 having a transparent common electrode 18 on a color filter layer 7 including sub color filters 7a to 7c and a black matrix 6 between the adjacent sub color filters 7a to 7c, and a second substrate 22 having a pixel electrode 17, a switching element “T” and array lines. Further, a liquid crystal layer 14 is interposed between the first and second substrates 5 and 22. The first and second substrates 15 and 22 are commonly referred to as a color filter substrate and an array substrate, respectively. The switching element “T,” for example, is a thin film transistor (TFT) disposed in a matrix arrangement and connected to a gate line 13 and a data line 15 crossing each other. A pixel region “P” is defined at a crossing portion of the gate line 13 and the data 15, and the pixel electrode 17 is made of a transparent conductive material disposed at the pixel region “P.”
The LCD device is driven by an electro-optical effect of the liquid crystal layer 14. Since the liquid crystal layer 14 is made of a material having dielectric anisotropy and spontaneous polarization, a dipole is formed in the liquid crystal layer 14 due to the spontaneous polarization when a voltage is applied. Thus, an alignment direction of liquid crystal molecules is changed according to a direction of an electric field resulting from the applied voltage. An optical property depends on the alignment state, and this phenomenon is a kind of an electrical light modulation. Therefore, the LCD device displays images by shielding or transmitting light using the electrical light modulation.
FIG. 2 is a schematic plane view showing an array substrate for a liquid crystal display device according to the related art. In FIG. 2, a gate line 13 and a data line 15 cross each other, and a thin film transistor (TFT) “T” is disposed at a crossing of the gate line 13 and the data line 15. A scan signal and an image signal are supplied to the gate line 13 and the data line 15 from an external circuit (not shown), respectively. The switching element TFT “T” is connected to the gate line 13, the data line 15, and a pixel electrode 17.
The TFT “T” includes a gate electrode 31, an active layer 32, and source and drain electrodes 33 and 35. The gate electrode 31 is connected to the gate line 13. The source and drain electrodes 33 and 35 are formed to overlap the gate electrode 31 are spaced apart from each other with the active layer 32 as a center. The active layer 32 is formed of one of amorphous silicon (a−Si:H) and polycrystalline silicon (p-Si). The source electrode 33 is connected to the data line 15 and the drain electrode 35 is connected to the pixel electrode 17 of the pixel region “P.” The pixel electrode 17 extends over the gate line 13, and a storage capacitor “CST” is formed between the overlapped gate and pixel electrodes 13 and 17. In another embodiment, the storage capacitor can be formed in the other structure.
When a scan signal is supplied to the gate electrode 31 through the gate line 13, the TFT “T” is turned ON. At the same time, an image signal synchronized with the scan signal is supplied to the pixel electrode 17 through the drain electrode 35. Thus, the liquid crystal layer 14 (of FIG. 1) on the pixel electrode 17 is re-arranged by a spontaneous polarization according to the applied image signal. When the scan signal is not supplied to the gate electrode 31, the TFT “T” is turned OFF. In the OFF state, charges of the pixel electrode accumulated during the ON state are undesirably discharged through the TFT “T” and the liquid crystal layer 14 (of FIG. 1). To prevent this undesirable discharge (leakage), the storage capacitor “CST” is used. The storage capacitor “CST” connected in parallel to the pixel electrode 17 (of FIG. 1) compensates the discharged charges to retain a data voltage of the image signal.
The image signal supplied to the pixel electrode 17 through the drain electrode 35 varies with effects of parasitic capacitances between terminals of the TFT “T.” A gate-source parasitic capacitance “CGS” is generated at an overlapping portion of the gate electrode 31 and the source electrode 33. A gate-drain parasitic capacitance “CGD” is generated at an overlapping portion of the gate electrode 31 and the drain electrode 35. When the active layer 32 is saturated, charges are concentrated on the drain electrode 35 and the gate-drain parasitic capacitance “CGD” increases.
FIG. 3 is a schematic plane view showing a thin film transistor of an array substrate for a liquid crystal display device according to the related art. In FIG. 3, a thin film transistor (TFT) “T” includes a gate electrode 31, an active layer 32, and source and drain electrodes 33 and 35. The active layer 32 overlaps the gate electrode 31 and the source and drain electrodes 33 and 35. When a scan signal is applied to the gate electrode 31, the TFT “T” is turned ON and an image signal is applied to a liquid crystal capacitor and a storage capacitor “CST” (of FIG. 2) through the drain electrode 35. The supplied image signal, which is a pixel voltage “Vp,” is retained even after the TFT is turned OFF. However, the pixel voltage “Vp” varies with a gate-drain parasitic capacitance “CGD” generated at an overlapping portion “D” of the gate electrode 31 and the drain electrode 33. A voltage shift “ΔVp,” defined by a difference of the pixel voltage “Vp” is commonly referred to as a level shift voltage or a kickback voltage. The kickback voltage “ΔVp” is a DC (direct current) voltage offset of the pixel voltage “Vp” AC (alternative current) driven due to the gate-drain parasitic capacitance “CGD.” The kickback voltage “ΔVp” can be expressed as follows.ΔVp=CGD·(VGH−VGL)/(CLC+CST+CGD)  (1),where CLC is a liquid crystal capacitance, CST is a storage capacitance, CGD is a gate-drain parasitic capacitance of an overlapping portion of a gate electrode and a drain electrode, VGH is a gate high voltage when a TFT is turned ON, and VGL is a gate low voltage when a TFT is turned OFF.
The kickback voltage “ΔVp” causes several disadvantages, such as a flicker, image sticking, and non-uniformity of brightness, thereby the display quality of an LCD device is deteriorated.